FPGA/SoC configuration and DDR3 memory routing with fly-by topology and length matching. Peripherals
Design for Manufacturing (DFM), generating Gerber files, and the ordering process. FPGA/SoC configuration and DDR3 memory routing with fly-by
Although many tutorials use Altium Designer or KiCad, the principles taught—such as high-speed routing and power distribution—apply to any ECAD software. The curriculum centers on the "ZettBrett," a custom
The curriculum centers on the "ZettBrett," a custom board featuring an AMD (Xilinx) Zynq SoC. and plane sizing. High-Speed Memory
The official course by Phil's Lab is a comprehensive, 11.5-hour program hosted on the FEDEVEL Education platform . While the full structured course is a paid professional resource, Phil's Lab provides a wealth of free educational content via YouTube that covers many of the same core principles used in the 2021-era curriculum. Course Overview and Learning Objectives
Layer stack-up design, controlled impedance, and signal integrity (SI) basics. Power (PDN)
Power Distribution Network design, including VRMs, decoupling capacitors, and plane sizing. High-Speed Memory